Non-Volatile-Memories (NVM) are extensively used in various portable applications, including mobile phones, music and video players, games, toys and other applications.
FIG. 1a depicts one such exemplary application of NVM, namely a removable storage device such as a SD card. However, the current invention is not limited to this specific use.
FIG. 1a depicts a system 100 comprising a host 110 and a data storage device 120 as known in the art. Data storage devices such as SD cards, USB sticks or other storage devices usually integrate NVM 130 and a controller 140 into a single package 120.
When connected to a host device 110, for example a personal or a laptop computer, communication between the data storage card and the host device commence. The controller 140 within the data storage device 120 manages data transfer between the host and the NVM 130 by serving as a gateway in both data transfer directions by writing to and reading from NVM 130. The data consists of user data and management data and files. Management files comprising addresses updates and files naming. The operating system that enables the communication between the host and the data storage device is DOS (Disk Operating System) based.
As known in the art, Host 110 may request to read information from data storage device 120. Host 110 is fitted with operating system capable of accessing external storage devices. It generally consists of Master Boot Record (MBR); Partition Boot Record (PBR); Folders information; and File Allocation Table (FAT). The MBR consist information regarding the data storage device including FAT location and size; and root directory location. Its location is always logic address 0 which is translated by the controller to a physical address in the memory die. Root directory is with constant table size, consisting 512 rows, each with a description of the files or folders existing in the disk. It includes name, size, first block location and type of file (file or directory).
Upon power-up, when connecting the memory card to the host or per user request to access the memory card, the MBR is addressed, the host generates a copy of the FAT in its memory and approaches to the root directory where information regarding the files is extracted (either located in the root folder itself, or more typically in a subfolder associated with the folder which appears in the root directory). Once the location of the first block of the requested file is identified, the rest of the blocks are sequentially pointed by the FAT. The FAT is owned by the controller and it uses logic addresses—the translation of the logic addresses to physical addresses is done by the controller that allocates both the data and the FAT in specific physical locations within the memory array.
In prior art, the controller manages the data access to the NVM die by page chunks, with size ranging between 512 B to 4 KB where NAND flash type memory is commonly used as the NVM incorporated in data storage devices. Typically to NAND flash memories, the array is not fully functional and some of the pages are defected and malfunction. As each page is characterized by unique address, the indexes associated with the defected pages are being kept in a dedicated area of the memory array. On power-up, the controller reads the information into its internal memory and uses it to avoid reading or writing to the defected locations.
A variety of controllers are available with different complexity, performance and cost. One of the main features characterizing these controllers is the internal memory capacity that allows handling stored information in the memory array, for example, conversion tables to indicate on the defected pages and their location. For low cost controllers, the internal memory space might be less than the minimum requirement to accommodate the maximum allowed number of bad blocks in typical NAND flash, commonly less than 2% of the memory array.
In methods of the art, in order to support field programming, the information associated with newly occurring defected blocks must be stored in a dedicated area before power-down. In standard NAND flash, this may be realized by writhing and re-writhing to a dedicated region in the memory array. The outcome of the above description is that after a few programming sequences, it may be possible that the loaded data is stored at non-continuous addresses space.
Other types of NVM memories that may be combined with a dedicated controller as a system is NOR flash or alternatively mask ROM (Read Only Memory) OTP (One Time Programmable), featuring perfect die characteristics with no need for bad blocks treatment due to tight production tolerances. In such a case the requirements from the controller are less demanding, as the ability to access a non continuous address space memory is not required.
The limitations that are associated with NOR memories relates to it being costly to produce compare to NAND flash and mask ROM OTP. Mask ROM OTP memories suffer from various deficiencies relating to the lack of field programmability capability, the limited die density, being typically less than 64 MB, and the long turn-around time as the processing time in the fabrication facility is long, typically 4-8 weeks. Furthermore, design to product phase may be long and costly as design errors may result with the need to generate new set of masks.
Other types of OTP memory that overcome the limitations associated with the traditional mask ROM technology are NROM and Matrix technologies. NROM technology for example, features field programmability capability, realizing much higher die density and may compact up to four times more bits per given die area by realizing the four per bit QUAD NROM technology.
In order to be compatible with NOR flash and mask ROM OTP controllers, NAND flash, NROM based memories and other types of memories that allow bad block occurrence, must present a continuous address space to its interface with the controller. Hence, realization of internal management of array deficiencies in NVM die, will relax the demand from the controller die.
U.S. Pat. No. 6,034,891 entitled “Multi-state flash memory defect management” to Norman, Robert discloses a defect management system for use in multi-state flash memory device, which has shift register which maintains input data to be written in defective memory location serially.
U.S. Pat. No. 5,671,229; titled “Flash eeprom system with defect handling”; to Harari, Eliyahou et al. discloses a computer system flash EEPROM memory system with extended life, which uses selective sector erasing, defective cell and sector remapping, and write cache circuit reducing faults.
U.S. Patent Publication No. 2006-0084219 to Lusky et al. entitled “Advanced NROM structure and method of fabrication” discloses a method to enable manufacturing the dual memory NROM memory die.